A substantial number of computing devices have been designed in accordance with a particular processing architecture originating with the IBM® Personal Computer introduced in 1981 (commonly referred to as the industry standard architecture, or ISA). Since that time, ISA has been augmented with numerous enhancements, notable among which is the Peripheral Component Interconnect (PCI) bus (promulgated by the PCI Special Interest Group), which provided a faster bus and added configuration registers providing a register-based protocol for detecting and configuring hardware devices that became a widely accepted part of ISA. However, despite such considerable progress in every technology associated with computing devices, various aspects of ISA remain undesirably in place, such as the I/O mapping of register sets and/or buffers of many hardware components at particular I/O and memory addresses.
As a result, even as memory mapping of register sets and buffers of newer hardware components at reassignable base addresses in both physical and virtual memory spaces have proven to provide numerous benefits, many hardware components are still required to also maintain accessibility to portions of those register sets and/or buffers at specific I/O addresses rigidly specified by ISA (including earlier versions of PCI configuration registers that have since become outdated). Among these hardware components are bus interfaces providing bridges between buses of different signaling, protocol and timing characteristics. Such bridges typically require configuration for use via sets of registers, just as the devices between which the buses and these bridges convey signals.
This strong adherence to the use of particular addresses at which to locate particular pieces of hardware, despite presenting various drawbacks, has long since been relied upon by the writers of both boot software and operating systems. Operating systems executing after boot software have not needed to receive more than minimal data concerning what hardware components are present in a computing system, since the ability to rely on accessing hardware devices at particular addresses specified by ISA (including PCI-styled configuration registers) has enable operating systems to perform their own hardware detection.
However, the growing prominence of processor circuits with no roots in ISA coupled with a desire to finally eliminate at least the more primitive vestiges of ISA has created a developing new situation in which upcoming hardware devices will no longer provide such register sets and/or buffers at such rigidly defined addresses. Instead, these register sets, buffers and/or equivalents thereto will be locatable at conceivably any address range in a virtual memory space. As a result, operating systems will soon require more data from the boot software. It is with respect to these and other considerations that the techniques described herein are needed.